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AMD Athlon 64 : HyperTransport technology - Getting acquainted
Last week we published the first in a three part series detailing the upcoming Athlon 64 CPU, to be launched on 23 September 2003. Then we looked at AMD64, the architecture behind Athlon 64, today we look at HyperTransport.

Just like their real life counterpart, buses in computers are one of the most ignored technologies when it shouldn't be. The example people make of having a Ferrari for a trip to the local supermarket as being overkill can be applied to computers. You can have the fastest processor in the world that can compute more data than anything before it, but if the infrastructure can't cope then you have the Ferrari situation, all the power and not enough road to use it. Wider and faster buses are the answer, but as easy as they are to say, the implementation of such a solution leads to many factors being considered such as economics and production viability. The consortium behind HyperTransport had to weigh these factors up when producing a technology that will be such an integral part of the Athlon 64.

Computer buses can be likened to a conventional road system. Their width affects the amount of data they can transfer in any one go, much like the lanes on a motorway. Sadly like in the real world, there is never enough lanes and the option of building further lanes or increasing the bandwidth isn't always an option. Bandwidth is the term given to quantify the amount of data that can pass in one operation or clock cycle and is measured against time. The unit of data varies, for example the bandwidth of a Internet connection maybe 100 megabits/sec, whereas the bandwidth between a 875P Northbridge controller and the RAM is 6.4 gigabytes/sec.

Typically buses consist of two sets of wires (usually called lines). One set transfer the control lines, the second transferring the data. The control line carries commands like 'read requests', acknowledgements and indications of what type of data is being transferred. Data lines 'carry' the data. HyperTransport, however, doesn't use two lines, instead it is a 'packetized' bus, which means that all the control commands and data travel on the same set of wires.

Buses come in two principle flavours, synchronous and asynchronous. The difference between the two is important as the primary performance vector of a bus; it's bandwidth is affected by the choice of whether it is synchronous or asynchronous. Most important computer buses are synchronous, which means that are timed to a clock. The rate of this clock is vital in the performance of the bus as transfers can only occur on a clock edge, or tick.

You might have already come to the conclusion that if a bus is wide and synchronized to a fast clock then you've got the perfect compliment to the Athlon 64. True, but implementing those ideals is extremely difficult and compromises have to be made in order to allow for cost and manufacturing viability. Like many things in computing, everyone knows how to make the perfect product but in doing so they shoot themselves in the foot. So it's how they make these compromises, cutting corners if you will, that makes a product good both in terms of profitability and functionality. HyperTransport does this in a variety of ways and the result of which is a very scalable, fast and easy to implement bus.

HyperTransport isn't a technology that was solely devised by AMD for use in Opteron or Athlon 64 machines. The HyperTransport Consortium, of which AMD are a member of have produced a bus that is suitable for a number of applications including embedded devices and network appliances such as switches and routers. HyperTransport is in use with the latest Macintosh G5 computers from Apple and have shown good performance in Opteron servers that have been available for almost six months prior to the Athlon 64's launch.

By using a narrow but high speed bus we see advantages such as easy routing, low power consumption and easy implementation. The latter is probably the most important as AMD need the motherboard manufacturers to support their new processor as soon as it comes out. By glancing at the popular motherboard makers that looks to be a certainty. HyperTransport is versatile too, allowing other buses like PCI, PCI-X to be connected through the use of 'tunnels'.

The basic HyperTransport system is extremely simple. You have a "host", which in the case of the Athlon 64 is the processor itself, the bus itself (you can think of it being a set of wires called links) and any I/O channels such as the PCI bus. Each link consists of two pins, one for input and the other for output.

The bus is synchronized to a 800MHz clock (800 million ticks per second) and has support for DDR memory signalling, effectively making it 1.6GHz. The bus is available in 2, 4, 8, 16 or 32-bit widths. The highest bandwidth would occur when you couple the 1.6GHz clock to a 32-bit link producing a bandwidth of 6.4GB/sec. That figure was calculated by :
(800MHz x 32 bits x 2) / 8 = 6,400 megabytes/sec

The initial figure was divided by 8 to get the number of bytes (1 byte = 8 bits).
The total throughput is double because HyperTransport has two pins, each giving the above 6.4GB/sec of bandwidth. So in all, the ultimate performance of the HyperTransport bus is 12.8GB/sec.

So lets take a moment to compare that figure to another popular bus, say PCI. PCI is extremely popular and has been around for a fair old while now. Nevertheless the most popular implementation runs at 33MHz and is 32-bits wide. The total bandwidth, using the same equation above, except for multiplying by 2 due to lack of DDR support would result in 132 megabytes/sec (MB/sec). The narrowest HyperTransport link on an Athlon 64 system, one running at 800MHz and being 2-bits wide produces a total throughput of 400MB/sec. The narrowest HyperTransport implementation is over three times faster than the PCI bus.

HyperTransport employs differential signalling, a method that by definition requires two copper wires. The result of each signal is the difference between the two signals in each wire. Low Voltage Differential Signalling or LVDS for short isn't a new technology and has been used in such things as SCSI buses for many years.

The advantages associated with LVDS are mainly reliability as opposed to performance, with risks of bouncing signals, interference and cross talk being all but eliminated. HyperTransport utilizes an enhanced version of this signalling which uses lower voltages in order to provide support for future core voltage and processor die size increase along with lower cost and reduced power requirements which is extremely important in mobile markets. AMD see HyperTransport technology being able to scale for the next 7-10 years.

When designing a bus scalability is a major factor in producing a technology that has a long lifespan. HyperTransport is able to scale both in frequency and bandwidth. As mentioned before, data links can be 2, 4, 8, 16 or 32-bits wide coupled to the ability to create ad-hoc HyperTransport systems where a certain part runs at, say 400MHz and others at 800MHz is possible without the need for devices or drivers gives added incentive to integrators for their support. Supporting lengths of up to 75 centimetres (varying with the number of layers on the PCB) the HyperTransport bus can have up to 32 devices attached to it.

Earlier we touched on the performance of a HyperTransport bus when compared to the aging PCI bus. Although it's clear which is the faster, AMD and other members in the HyperTransport consortium know that they can't replace a bus that has been around for almost a decade overnight, and alienating users will only result in a slower acceptance of HyperTransport and technologies that use it such as the Athlon 64.

For that reason HyperTransport has full software compatibility with the PCI bus and utilizes tunnels to enable communications with other popular buses such as AGP, PCI-X and Gigabit Ethernet amongst others. The idea of integrating with existing technologies runs throughout the Athlon 64 theme and it's choice of supporting technologies.